In an integrated circuit (IC), a System on Chip (SoC) may integrate a memory device, a logic device and a semiconductor IP on a chip. To reduce power consumption, a variety of voltages are used in different components. To allow the devices to exchange data, a level shifter or translator shifts the output voltage levels of one device or component to an appropriate input voltage level of a counterpart device. For example, when external voltages VDDL at 1.2 V and VDDH at 1.5 V and ground GND or VSS are supplied to a device in a chip, devices operating at 1.2 V must have outputs shifted to 1.5 V before being input into devices operating at 1.5 V. Conversely, devices operating at 1.5 V must have outputs shifted to 1.2 V before being input into devices operating at 1.2 V.
FIG. 1 shows a single supply level converter. The level shifter shown in FIG. 1 includes an input inverter connected to an input terminal 10 and including a PMOS 16 and an NMOS 18, and an output inverter connected to an output terminal 20 and including a PMOS 22 and an NMOS 24. The input inverter and the output inverter are connected between ground and VDDH. That is, the level shifter shown in FIG. 1 shifts a low input voltage to a high output voltage only using a high voltage VDDH without using a low voltage VDDL.
The reason a level shift is possible is because the source (that is, a node N2) of the PMOS 16 included in the input inverter is connected to VDDH via an NMOS 12 which is configured in the form of a diode. Since the source of the PMOS 16 receives a voltage obtained by subtracting a threshold voltage Vt of the NMOS 12 from the high voltage VDDH, the same effect as supplying the low voltage VDDL to the input inverter can be obtained.
Since the source of the PMOS 16 included in the input inverter is also connected to VDDH via a PMOS 14 and the gate of the PMOS 14 is connected to the output terminal 20, the PMOS 14 is turned on when the output terminal 10 is low (that is, a low level signal is input to the input terminal 10) such that leakage current is reduced.
The level shifter shown in FIG. 1 is advantageous in that only a single voltage source is used and a leakage current characteristic is excellent.
However, if a voltage difference between a low voltage source and a high voltage source is large, the level shifting may become unstable or a malfunction may occur. This is because the voltage level of a node N2 (that is, the low voltage VDDL) is restricted by the threshold voltage of the NMOS 12 due to a diode structure in which the gate and drain of the NMOS 12 are connected to VDDH. Accordingly, the threshold voltage of the NMOS 12 having the diode structure has influence on the operation of the level shifter.
The level shifter shown in FIG. 1 is susceptible to electrostatic discharge (ESD) because the gate of the NMOS 12 is directly connected to the high voltage source VDDH.
FIG. 2 shows a level shifter. In FIG. 2, NMOSs 32 and 38 and PMOSs 34 and 36 form a NOR gate. When HOLD is high, an output node N1 of the NOR gate is held low. When HOLD is low, the output node N1 of the NOR gate is the logical inversion of an input signal IN. NMOSs 40 and 42 and PMOSs 44 and 46 form another NOR gate. When HOLD is high, the output node N2 of this NOR gate is held low. When HOLD is low, the output node N2 of this NOR gate has the same value as the input signal IN. A PMOS 48/NMOS 52 and a PMOS 54/NMOS 56 form a cross-coupled inverter which is a bit storage cell. When HOLD is high, both NOR gates have a low output value, the NMOS 50 and the NMOS 58 are turned off and thus the cross-coupled inverter maintains the state of the output signal OUT. When HOLD is low and the output node N1 is high, the NMOS 58 is turned on and the output signal OUT is pulled low. The inverter formed by the NMOS48/NMOS52 reinforces this condition. When HOLD is low and the output node N2 is high, the NMOS 50 is turned on, the input to the inverter formed by the PMOS 54/NMOS 56 is driven low, and the output signal OUT is driven high. The inverter formed by the PMOS 48/NMOS 52 reinforces this condition.
Since the level shifter shown in FIG. 2 uses two voltage sources including a low voltage source Vdd and a high voltage source Vdd_H, there are restrictions in the implementation and design of a cell. Since a low voltage source and a high voltage source are required when designing the cell, the size of the cell increases. The cell should be connected to both the low voltage source and the high voltage source, regardless of the position of the cell. Due to such a restriction, the cell should be placed in a boundary between a circuit block which operates by a low voltage and a circuit block which operates by a high voltage. Since a source line connected to the voltage source is placed in a routing region, it is disadvantageous in view of routing. Since an external signal is initiated at the cell, a block, in which the cell is placed, requires an additional area due to power routing of the low voltage source even at the time of performing a place-and-route (P&G) algorithm. In addition, there is a restriction in routing due to the restriction on the position of the cell.
FIG. 3 shows a single supply level shifter. The level shifter shown in FIG. 3 includes an input stage 60 connected to a high voltage source VDDA and an input terminal IN and an output stage 62 connected to the high voltage source VDDA and an output terminal OUT. The input stage 60 includes an NMOS 64, a PMOS 66, and a capacitor 68, and the output stage 62 includes two NMOSs 70 and 72 and two PMOSs 74 and 76. When the signal of the input terminal IN is high (that is, VDD), the NMOS 72 of the output stage 62 is turned on and the drain of the NMOS 72 is pulled down to a reference voltage VREF. Then, the PMOS 66 of the input stage 60 is turned on such that the gate of the NMOS 64 is pulled up to VDD, and the NMOS 70 of the output stage 62 is turned on such that the output terminal OUT becomes VDDA. That is, the low voltage level of the input terminal IN is shifted to the high voltage level of the output terminal OUT. Next, when the signal of the input terminal IN is pulled down to the low level, the gate of the NMOS 64 is initially held at VDD. Accordingly, the signal of the output terminal OUT is pulled down to the low level by the NMOS 64 which is turned on. The PMOS 66 of the input stage 60 prevents the NMOS 64 from being turned off before the output terminal OUT is completely discharged. At the same time, the NMOS 70 of the output stage 62 is turned on to provide a positive feedback for the discharge of the output terminal OUT.
The level shifter shown in FIG. 3 can shift the voltage level between the input and the output using a single voltage source, but requires an additional circuit for the reference voltage source VREF. Such an additional circuit uses additional area when designing a standard cell and degrades routing efficiency of the signal input to the reference voltage source VREF.